This invention relates to printed circuit boards and more particularly to printed circuit boards for use in high-speed computer bus applications.
Printed circuit boards having a plurality of layers, each including various conductive planes and printed circuit traces are used widely throughout the computer industry. These boards enable a large number of connections between circuit components to be made in a relatively small surface area. Typically, boards are constructed by laying conductive material (typically near-pure copper), in solid or deposited form, on a layer of resinous material that is typically between three and ten thousands of an inch thickness. The material is selectively etched using known techniques, which can include photolithographic processes, to create a circuit traces. The individual etched layers are then adhered into a precisely positioned sandwich to form a complete multi-layer printed circuit board. Connecting pins from circuit components (chips) pass through the layers and contact a predetermined trace on one of the layers. Solder and/or other electrical connectors form an electrically conductive bridge between the chip pin and the appropriate trace.
It is generally desirable to make the traces as narrow as possible (no less than about 0.005 inch) so that a larger number of traces can be formed upon a given layer.
However, in creating traces, as well as spacing layers from each other, the resulting impedance characteristics of the various layers may be altered significantly. A variety of design rules and equations exist for accurately predicting impedance for a given set of traces in a multi-layer circuit board. In most instances, it is desirable to lower the impedance of circuit board traces to improve signal transmission. This is particularly true of a data bus carrying Protocol Control Information (PCI) known generally as a xe2x80x9cPCI bus.xe2x80x9d Such a PCI bus typically requires a low-impedance pathway on the order of approximately 55 Ohms. However, certain signal arrangements require higher impedance, such as a Small Computer System Interface (SCSI) interconnection used largely for disk controllers. In general, by locating the power and ground planes close to an adjacent layer, a relatively low impedance for signal-carrying traces on that adjacent layer is maintained. Conversely, spacing the power and ground layers more distant from adjacent layers results in higher impedance for the signal traces adjacent layers. Generating appropriate impedance for a given circuit trace involves a number of well-known-but-complex calculations taking into account various variables. These variables include the spacing between board layers, distance from a ground and/or power plane, the relative thickness and height of the trace and the dielectric of the board material. An overlying technique entails the widening and narrowing of the traces to produce, respectively, lower or higher impedance therein. In one example SCSI traces are formed with widths as small as 0.004 inch. This taxes board manufacturing efficiencies and reliability.
One effort to modify the impedance of respective layers is shown is FIG. 1. This diagram is representative of a product available from Sun Microsystems as part of its Sparcstation 4 and Sparcstation 5 products. A circuit board 100 generally representative of the Spark Station product is shown in FIG. 1. It includes five separate board layers according to this example. The insulating structural board material for each layer is typically formed of identical materialxe2x80x94a fiberglass product well-known in the art and commercially designated as FR-4. The layers 102, 104, 106, 108 and 110 as shown from top to bottom. Disposed between each layer, and on the top and bottom faces of the board, is a circuit trace of predetermined shape and size. A dividing line 112 delineates a specialized high-impedance section 114 (to be described further below) from the remaining lower/low-impedance board section 116. In the low-impedance board section 116, the topmost trace 118 and the bottommost trace 120 are each low-impedance signal traces. They are located adjacent a ground (GND) plane 122 and an opposing (PWR) plane 124 on directly adjacent layers. By maintaining the ground and power planes in close proximity to the signal traces 118 and 120, a lower impedance can be attained. Internal signal traces 126 and 128 are also located on opposing sides of the central layer 106. These are also in close proximity to the ground and power planes 122, 124 respectively. Hence, the board section 116 maintains its signal traces all at lower impedance. Conversely, the specialized high-impedance section 114, which is typically adjacent SCSI bus connection (described below), benefits by spacing the ground and power planes 122 and 124 at a further spacing from the SCSI traces 130 and 132 located on the top and bottom of the board respectively. This greater spacing is accomplished by stepping each of the ground and power planes 122, 124 inwardly so that they each confront the central layer 106 of the board 100. Accordingly, a larger spacing d between the ground and power planes 122, 124 and the outer SCSI traces 130, 132 is attained.
In this example, the ground and power planes are xe2x80x9csteppedxe2x80x9d by providing a series of connections known as vias that are formed according to conventional techniques through the respective board layers 104 and 108 enabling the electrically connected steps 134 and 136 to be formed. The area between board layers 102 and 104 and/or 108 and 110 is a xe2x80x9cdead zonexe2x80x9d or xe2x80x9cvoidxe2x80x9d as shown by the dotted lines 140 and 142. Generally, no traces are present in this void area between board layers. In general, the prior art circuit board contained traces having a variety of etch widths to further vary the impedance characteristics. The arrangement detailed in FIG. 1 places the SCSI traces on the external faces of the board. It would be desirable to locate multiple SCSI layers on the internal faces of the board, as this enables more predictable control of impedance and better shielding of circuit traces. In addition, it is desirable to provide a simplified trace construction in which all circuit traces are formed with a reasonably small but constant width to increase packing efficiency, while not requiring overly small widths (under 0.005 inch, that tax the reliability of the board etching process. In addition, it is desirable to provide a board arrangement that enables a greater number of layers to be stacked with greater control over the impedance of traces on the various layers. Accordingly, is an object of this invention to provide such an improved multi-layer board of structure.
This invention overcomes the disadvantages of the prior art by providing a multi-layer printed circuit board defining a high-impedance section thereon in which power and ground traces extend stepwise toward respective upper and lower external layers while two or more SCSI layers are located within the center of the stack of layers separated from the power and ground layers by at least one xe2x80x9cdead zonexe2x80x9d or xe2x80x9cvoidxe2x80x9d layerxe2x80x94the void layer being produced by the external step of the power and ground layers within the high-impedance section.
According to a preferred embodiment, the board includes at least nine board layers, composed of a resinous materialxe2x80x94typically a fiberglass composite such as commercially available FR-4. The high-impedance SCSI circuit trace layers are located in the central portion of the board while low-impedance signal layers can be located on the external faces and also on all layers outside the high-impedance section (e.g. within the low-impedance board section.
All traces can be formed with a width of approximately 5-7 thousandths of an inch (5-7 mils) while maintaining a desired impedance in a range of between approximately 55-85 Ohms.